A cross-sectional view of the structure of VDMOS transistors disclosed in U.S. Pat. No. 4,682,405 is shown in FIG. 1. The VDMOS transistors have an N.sup.+ substrate 10, which forms the drain electrode of the transistors, an N type epitaxial layer 11, a V-shaped trench 12, a P type body region 13, an N.sup.+ source region 14, a gate electrode 15, gate oxide 16, an oxide layer 17, and a source electrode metal contact 18. In this structure, the V-shaped trench. 12 is used to reduce the dimension of the entire VDMOS transistor. However, the N.sup.+ source region 14, the P type body region 13, and the N.sup.+ substrate 10 form a vertical parasitic NPN transistor, and since the vertically projected area of the N.sup.+ source region 14 is relatively large, the leakage caused by the parasitic NPN transistor and the propensity to latch-up are relatively large.